1. Field of the Invention
The present invention relates to a mounting configuration of a semiconductor integrated circuit.
2. Description of the Related Art
Various semiconductor substrates suitable for different applications are available for producing a semiconductor integrated circuit. Most of the semiconductor substrates are N-type semiconductor substrates containing N-type impurities such as phosphorus and P-type semiconductor substrates containing P-type impurities such as boron.
When an N-type semiconductor substrate is used for producing a semiconductor integrated circuit including a CMOS circuit, a configuration as illustrated in FIG. 4A is employed. Specifically, a P-type well region 6 is provided in an integrated circuit chip 2 using an N-type semiconductor substrate 2, and an N-channel MOS transistor (hereinafter referred to as NMOS) 102 and a P-channel MOS transistor (hereinafter referred to as PMOS) 101 are integrated on the N-type semiconductor substrate in this P-type region and in the other region, respectively. Then, the NMOS 102 and the PMOS 101 are connected by metal wiring to constitute a circuit. In this case, in order to reliably separate and insulate the P-type well region and the N-type semiconductor substrate from each other, the potential of the P-type well region is fixed to a minimum potential (hereinafter referred to as VSS potential) of the semiconductor integrated circuit and the potential of the N-type semiconductor substrate is fixed to a maximum potential (hereinafter referred to as VDD potential) of the semiconductor integrated circuit. In this way, a forward current is prevented from flowing in the N-type semiconductor substrate and the P-type well region.
Specifically, all terminals in the circuit which have the VDD potential, including a source terminal 4 of the PMOS, are connected to the N-type heavily doped diffusion region 13 provided on the N-type semiconductor substrate for electrically connecting the potentials, and define a VDD pad 103. In the same way, all terminals in the circuit which have the VSS potential, including a source terminal 5 of the NMOS, are connected to the P-type heavily doped diffusion region 12 provided in the P-type well region, and define a VSS pad 104.
On the other hand, in the case of integrating semiconductor elements on a P-type semiconductor substrate, as illustrated in FIG. 4B, all terminals in the circuit which have the VSS potential, including a source terminal 5 of the NMOS, are connected to the P-type heavily doped diffusion region 12 provided for electrically connecting the potential to the integrated circuit chip 1 using the P-type semiconductor substrate 1. In the same way, all terminals in the circuit which have the VDD potential, including a source terminal 4 of the PMOS, are connected to the N-type heavily doped diffusion region 13 provided in the N-type well region 7.
In the case of the above-mentioned configurations, the semiconductor integrated circuit using an N-type semiconductor substrate has the VDD potential in the entire N-type region inside the semiconductor substrate and along the bottom and side surfaces of the semiconductor substrate excluding the element formation region on the surface of the semiconductor substrate, and the semiconductor integrated circuit using a P-type semiconductor substrate has the VSS potential in the entire P-type region inside the semiconductor substrate and along the bottom and side surfaces of the semiconductor substrate excluding the element formation region on the surface of the semiconductor substrate. Accordingly, when the semiconductor substrate is diced into individual chips through a dicing step and the like, a semiconductor substrate having the VDD potential or the VSS potential is exposed in regions other than the surface of the semiconductor substrate.
For various reasons, the N-type semiconductor substrate and the P-type semiconductor substrate are used for different applications. The selection of the substrates depends on, for example, the performance of a mounting element such as a transistor and the circuit requirements as well as the structural convenience of a module substrate and a module circuit for mounting the semiconductor integrated circuit device.
One possible case is to control a back bias of a specific MOS transistor in the semiconductor integrated circuit in view of restrictions of circuit operation. For example, in FIG. 4A, the control of a back bias of the NMOS transistor from a circuit can be realized by disconnecting the P-type heavily doped diffusion region 12 in the P-type well region 6 of the specific NMOS 102 from the source of the NMOS and connecting wiring extended to the P-type heavily doped diffusion region to a circuit for controlling the back bias. In this way, in the case of the N-type semiconductor substrate, the P-type well region in which the NMOS is mounted can be separately and individually formed, and hence the potential of a specific P-type well region can be changed to control the back bias of the NMOS.
By the way, in the case of using a P-type semiconductor substrate as illustrated in FIG. 4B, all the P-type regions in which the NMOS is mounted are connected to have the same potential, and hence the control of a back bias of a specific NMOS cannot be conducted. Under those circuit requirements, the N-type semiconductor substrate is selected.
FIGS. 2A and 2B illustrate a semiconductor integrated circuit using an N-type semiconductor substrate mounted in a package after separation into individual chips through a dicing step and the like. FIG. 2A is a schematic cross-sectional view, and FIG. 2B is a plan view showing a lead frame. In FIG. 2A, the diced semiconductor integrated circuit chip 2 is bonded on a die pad 9 in a molded metal lead frame via an adhesive paste 8, and the die pad is electrically connected to a metal VDD pad 103 formed on the semiconductor integrated circuit chip via a bonding wire 10 formed thereafter. The semiconductor chip has an N-type well region 6 and a P-type well region 7, and is covered with mold resin 11. As exemplified in FIG. 2B, in general, the semiconductor integrated circuit chip has a plurality of pads (103, 104) for electrical connection. Thus, leads (terminals) corresponding to the pads are prepared also on the lead frame side, and the pads and the leads are connected via bonding wires.
In this case, in general, the adhesive paste uses a silver paste in order to obtain electrical connection between the die pad provided under the semiconductor integrated circuit chip and the exposed semiconductor substrate. The semiconductor integrated circuit chip in this example uses an N-type semiconductor substrate, and hence the die pad 9 bonded to the N-type semiconductor substrate via the silver paste is set as a VDD terminal as it is. Then, as illustrated in FIG. 2B, the die pad is connected to a VDD pad 103 formed on the surface of the semiconductor integrated circuit chip via the bonding wire.
A method of bonding the semiconductor integrated circuit chip to the die pad and electrically connecting the die pad by the bonding wire is disclosed in, for example, Japanese Patent Application Laid-open No. Hei 5-160333.
However, in the case where the polarity of the semiconductor substrate is changed, the conventional mounting method has the following problem.
For a wider variety of lineup of the semiconductor integrated circuit device, if there are restrictions that only the semiconductor integrated circuit device needs to be replaced by one having new performance without changing a module in which the existing semiconductor integrated circuit device is mounted, it is necessary to match attributes of a terminal of the existing module and a terminal connected to the die pad of the semiconductor integrated circuit device (pin-compatibility). In this case, the largest factor of inhibiting the pin-compatibility is the difference in polarity of the semiconductor substrate.
Using FIGS. 3A and 3B, for example, it is explained that the die pad used in FIGS. 2A and 2B, which is an example of using an N-type semiconductor substrate, cannot mount a semiconductor integrated circuit chip 1 having the same function as that produced by using a P-type semiconductor substrate. FIGS. 3A and 3B illustrate a semiconductor integrated circuit using a P-type semiconductor substrate mounted in a package. FIG. 3A is a schematic cross-sectional view, and FIG. 3B is a plan view showing a lead frame. Since the potential of the P-type semiconductor substrate is set to the VSS potential as illustrated in FIGS. 3A and 3B, the die pad 9 connected to the P-type semiconductor substrate via the silver paste is also a VSS terminal as it is, and it is necessary to change the VDD terminal in FIG. 2B to the VSS terminal in the example shown by FIG. 3B. Accordingly, in order to use the same die pad, it is necessary to make circuit design intended for the N-type semiconductor substrate, but such circuit design cannot be made in some cases because of circuit requirements. Thus, the design flexibility is significantly hindered.
One of the most reliable methods is a method of designing and manufacturing, for each module substrate for mounting, a new die pad suitable for pin arrangement of the existing module without adding a design change in the semiconductor integrated circuit device. This method, however, has a disadvantage that the cost and the launch and check periods for production of a new die pad are necessary, leading to the cost increase also in terms of volume efficiency.
A method capable of designing a semiconductor integrated circuit chip regardless of pin attributes of the existing module substrate and easily realizing pin-compatibility in a mounting step has thus been sought after.